STANDARDIZED CLAIM CARD: CLAIM-04-GRID

Document ID: CLAIM-04-GRID
Version: 1.0.0-gold (Pre-Registered)
Parent Paper: Sub-Cycle Grid Defense: Sub-Cycle Micro-Shedding, Inverter Coordination, and Millisecond Frequency Regulation in High-Density AI Campuses
Date: Tuesday, September 22, 2026
Status: POWER SYSTEMS RECONCILED & MAPPED
SHA-256 (Locked Paper): 0f5f6572f15d3fd7d610ddd24ab6560af1af77831ed7f60cbd73c8febdb0c7c8

1. Exact Claim

ATESO CAVI (Compute-As-Virtual-Inverter) architecture executes a 45 MW step load shed within one AC cycle (16.7 ms actuation, 35–52 ms end-to-end) under under-frequency events (5–7× inside ERCOT’s 15-cycle Fast Frequency Response requirement), providing autonomous primary frequency damping ($\zeta = 0.49$, phase margin $\phi_m = 51.4^\circ$) and sustaining a 15-minute continuous FFR hold entirely through silicon compute compaction without cycling or degrading facility UPS batteries (UPS stays on float, zero incremental storage CapEx), while constraining inductive transients to $\le 57.1\text{ V}$ at 13.8 kV ($0.060\%$ of 95 kV BIL).

2. Scope & Target Architecture

• In-Scope: High-density AI data center campuses ($\ge 100\text{ MW}$ facility, 13.8 kV medium-voltage distribution, Class B elastic batch inference and training workloads).
• Out-of-Scope: Critical life-safety infrastructure, un-tiered computing facilities without granular core power-gating, or unsanctioned autonomous islanding without utility interconnection agreement.

3. Baseline & Standards Mapping

• Standards Mapping: Designed against and mapped to ERCOT Nodal Protocols §2.3 Fast Frequency Response (FFR-1) (trigger at 59.85 Hz, response requirement $\le 250\text{ ms}$, 15-minute hold) and IEEE 2800-2022 (Standard for Interconnection and Interoperability of Inverter-Based Resources).
• Conventional Baseline:
  • Traditional Demand Response (OpenADR): $5\text{ to }15\text{ minutes}$ latency.
  • Backup Diesel Generation: $10\text{ to }30\text{ seconds}$ start time.
  • Dedicated BESS: Sub-second response, but incurs severe battery cell degradation ($0.5\% - 1.5\%$ capacity loss per 100 deep cycles) costing millions annually.

4. Fundamental Electrical Formulations

• Maximum Inductive Flyback Voltage: $$V_{\text{flyback}} = L_{\text{leak}} \left( \frac{di}{dt} \right)_{\max}$$
  • $L_{\text{leak}} = 0.505\text{ mH}$ (Substation step-down transformer leakage inductance).
  • Maximum rate of current shed: $\left( \frac{di}{dt} \right) = \frac{1{,}882.7\ \text{A}}{(1/60)\ \text{s}} = 112{,}960\ \text{A/s} = 113.0\ \text{kA/s}$ (staggered across one full 16.67 ms AC cycle).
  • $V_{\text{transient}} = L_{\text{leak}} \frac{di}{dt} = 0.50516 \times 10^{-3} \times 112{,}960 = \mathbf{57.1\ \text{V}}$ nominal ($0.72\%$ of nominal $7{,}967\text{ V}$ phase voltage, and $\mathbf{0.060\%}$ of the $95\text{ kV}$ Basic Lightning Impulse Level [BIL]).
• Silicon-Only 15-Minute Hold:
  • Class B elastic batch compaction accounts for $65 - 75\text{ MW}$ of the facility’s $100\text{ MW}$ load. Compacting token queues sustains the $45\text{ MW}$ reduction for $>15\text{ minutes}$ with zero BESS battery discharge.

5. Falsification Criterion

The claim is falsified if an IEEE-standard transient network simulation shows that shedding 45 MW across 1,000 staggered inverter stages in 16.6 ms causes voltage flyback $>500\text{ V}$ ($>0.5\%\text{ BIL}$) on a 13.8 kV bus, or if the 45 MW reduction cannot be sustained for 15 minutes without dropping active training checkpoints or engaging battery storage.

6. Safety, Regulatory & Compliance Disclaimers

• Research Prototype: CAVI is an advanced engineering architecture and simulation model. Full physical deployment requires formal Interconnection Study (IA) and coordination with the Regional Transmission Organization (RTO/ISO).
• Operator Override: Hard physical lockouts and utility SCADA overrides have absolute preemptive priority over autonomous micro-shedding logic.